
Data cell fails to update in one tick when clocked with red alloy wire
Opened this issue ยท 1 comments
- MC 1.7.10
- Forge 10.13.4.1558
- Only mods installed are the latest TJP & PR on Curse as of this post.
Setup
- Generate a 2 (redstone) tick / 5Hz clock signal with a not gate or invert cell.
- Feed this signal to the enable input of a data cell.
- Apply a 'on' signal to the data input of the data cell; it won't be propagated to the output.
Extra information
- It works as expected when ordinary redstone is used for the clock signal.
- Red alloy wire will work if the clock signal was generated with a not gate and only travels through one wire length to reach the data cell. Perhaps a condition for it to occur is that the signal strength be less than the maximum.
- Transparent latches work as expected with red alloy wire.