This would be a new series of gates in the theme of the current '2D' array cells with an additional rail along the vertical axis.

2D array cells are very useful but because they effectively have 2 I/O options it's difficult to fit any sort of logic into arrays; this has been done with several cells not found in RP2, but only by breaking the rail and effectively breaking the array dichotomy; in effect these are not actually array cells; though they are very useful they serve as boundaries between arrays, which can be achieved with existing tiles. The AND cell is a simplification of 2 NOT gates and a Buffer or Invert cell.

With the addition of a vertical rail, that would be making these full block gates with 6 I/O faces and 3 I/O options, it becomes possible to perform logical operations with 2 inputs and 1 output, the reverse, or even lesser operations with one or two NULL rails. This is 'technically possible' with a single gate currently, but it also requires a 3x3x2 block space per cell, and quite a few covers.

I've used bundles in this example build because it's what I had on me, I'm in the process of making array behavior ICs for bundles. Blue and Green are horizontal, Red is vertical. (of course looking at it now I see a bit I forgot)

To some extent this could even be achieved by a 3D array chassis block, that normal logic tiles get placed into. Instead of making individual variants of all the eligible logic tiles. I cannot at this point in time imagine how to manage that conveniently without a GUI.

I am keeping all new gate requests in mind. I will consider implementation after the fabrication system is rewritten, as there will be many possibilities it will open.

For this in particular, I am not really sure what it would accomplish. I understand that you want to run signals up and down, but gates are not coded to handle that type of propagation. I'm not sure it's worth the massive work it would take to make it so..

Upon further consideration, I will not be adding a full block gate, as there is not enough use cases for it.

I have been unable to construct a convincing example of their worth, I still believe in the idea but.... yea. I had several ideas for gates with a vertical rail and independent contacts on on the other 4 faces, but as I argued that doesn't really count as a cell because it serves as a boundary to the array; one example of that is memory blocks, you could use the rail as the clock to tick stacked memory channels and step data deeper into the set; then you can put data in or out the sides. in whatever configuration, and tick the rail of each column in a sweep to grab the data from the column to the left.

This is wholly unnecessary, I have built exactly that in the past, it's just a massive pain to structure it all, in RP2 you needed a 4 block deep platform N columns long and 1 block tall per channel, I've already found that I could reduce that to 3 blocks deep in Project Red because framed bundles can takeup insulated wire directly now. Having a vertical rail would replace the horizontal clock line on each row, and allow a more ordered update progression where the row clock is just kinda hoping that all the ticks work out so each gate picks up the intended value from the other gate and not the new value or some weird quantum value as sometimes happens when you're building a really bad idea on a really big scale.

(that memory thing: http://i.imgur.com/oNJFt.jpg )
(bad ideas on a massive scale: http://i.imgur.com/tVSlx.jpg && http://i.imgur.com/YhTTH.jpg )

A couple of general purpose concepts that would aid everything discussed here are "insulated framed bundled cable", that only links with like-colored blocks of that thing I said so you don't need to run walls of covers to isolate framed bundles; and the same thing with framed redwire but then allow it to run directly into gates without needing a surface mount wire, this could be handled on either side of the face by having a lead pop into existence when the side that handles it detects it's neighbor, bridging from the center of the shared face to the side the gate is against.

all that combined and switching to a horizontal surface, the memory cell would be laid out as a square, a rail bridges all the gates in a column and serves as the clock tick, you input state at the left (for example) and when the clock is ticked on a column it sets it's right side output to the value being received on it's left side, and also outputs that value upward, where you take up the value into a bunch of isolated framed redwire leads, which will need cover isolation across the rows because each row is a single color, but across the columns they'll be fine, and then you have a layer of isolated framed bundles taking up the isolated framed redwire, which doesn't require any cover isolation.

This reduces the build from 4 blocks of surface with 3 blocks of cover isolation and a total depth of 5 blocks in RP2; to 1 block of surface and 1 block of cover isolation with a total depth of 3 blocks, plus a small amount of additional circuitry at the end of the rails to handle ticking the clock in order. But it also reduces it from a layered arrangement to a 2D block arrangement.
(in case it's ambiguous, I'm using "block of surface" to denote a block space where something is placed on an interior face and must have something there to be placed against, gates, redwire, and bundles occupy a "block of surface", framed cabling does not)

I don't remember all of the gates clearly right now but any of them that use a clock tick pass-along mechanic like state cells, I think my example here was transparent latches, there's probably other applicable blocks.....

That's my best shot, excited for the fabrication system rewrite, love what it offers, not so fond of using it....