One side has bundled input for adress (ADR). Second side is bundled data IO (DIO). Third side is read enable signal (RE). 4.side is write enable signal (WE). When 1 is at RE, DIO will output data stored at adress location from ADR. When 1 is at WE, data at DIO will be writen to adress location from ADR.

Adress width could be configurable with screwdriver and max adress width is 16 bits. RAM with maximum adress width whould have 2^16=65536 adresses. Each adress stores 16 bits. So RAM whould need max 131072 bytes of storage which might not be a good idea to store as NBT so it might be good to store it as separate file in save directory which whould allow relatively easy editing of memory contents.

This gate whould be usefull when building redstone CPUs as you could have whole RAM in one block without using computercraft (which can be quite laggy).

+1 on this, I know it could be "made" with a bunch of circuits but its very difficult managing it with IC chips at this state and logic blocks themselves.

But you whould need to place X of these to make RAM with X adresses and that whould be quite painfull and impractical for RAM with even just 256 adresses (I did that once with custom ICs-I have made a programmable decoder for that. But it was huge, slow to build-I even made a counter which I used to program the decoders and increment the adress so that I could build it faster. If you whould want to build even bigger RAM you whould need to start using some sort of bus repeaters(bidirectional) to amplify the signal-that whould slow it down. And in the end such huge RAM whould take up more game memory than single block RAM. And it whould also lag more.

If you whould want to use smaller memory, you whould just configure the RAM gate to use less adress bits and it whould then use less game memory becouse it whould not need to allocate as much.

Becouse of all that I think the RAM gate is needed.

Sorry I accidentally closed this when I was commenting- I was writing on phone and missclicked.

This would definitely be nice, although if this seems like it puts too much functionality into one gate, then maybe a bundled decoder would be a good alternative. By this I mean it would take a bundled cable input and output a signal if the bundled cable inputs match the configured inputs on the gate. This would also be more memory friendly since you wouldn't be allocating 64 KiB of memory for every block like you would with a RAM block.