Is or will there be any support for nesting ICs? This would really be great for those of us who want to make a 16-bit microprocessor in a single chip (is that just me?)

Yes, it will be supported eventually. But there will definitely be a limit in place to ensure that the calculations can still be done in a reasonable amount of time. I wouldn't expect to be making anything crazy like an entire microprocessor, but we'll see what kind of optimizations I can come up with.

You could then add pre-made or hard-coded IC circuits as loots or villager trades.
These hardwired circuits would use direct java code logic rather than compiled logic from player-made custom ICs.
Would allow these complex ICs to assemble even more complex player-made ICs.

Have a look at Robot Odissey from the Learning Company that has been remade as Droid Quest in Java https://github.com/ThomasFooteDQ/DroidQuest

It has player-made ICs assembled from logic gates and wirings, and hard-coded ICs.
It supports 3 levels of nesting.
And the original game ran on a 1MHz 6502 CPU at roughly 1 robot move per second.

The idea is to have the compiled logic optimized into actual java byte-code so it runs natively. It's not there yet but in its current state its fairly efficient. I have not had many people do extensive stress tests yet though. But yea, that could be a way to do it. Once nesting is supported, we can have crazy hard-coded ICs that you can drop in.

More hardcoded stuff would be nice for world loading performance. I've made a really naive implementation of a 32 bit multiplier that uses 47x popcount circuits, 31x 16-adder circuits, and 16x 4-bit adder to have a result within 66 ticks. Takes 500 years to load :)

Maybe you could compile all ICs into bytecode by using self modifying code. For example: when you initialize the IC (place block), the game compiles custom java bytecode for that IC (similar to how coremods can modify loaded classes you could modify the code of IC). With that you could have speed benefits of hardcoded logic gates even with custom logic gates.

That could also be the case for nested ICs, so if you make an adder or something it would be effectively as fast as a hardcoded adder circuit in your larger IC, which would allow more levels of nesting without incredible lag (or at least, significant lag when you place it and then fairly fast processing of inputs).

This is being discussed here: #1616