If I move components (like NOR gates, constants etc) into the middle of the grid the design requires a lot more memory cards to assemble compared to having all components (except the output - see issue #10) in the first row.

It would be nice if only used grid cells are counted for design cost.

Thats because currently all preceding and gaps of unused grid cells are filled with virtual constant components (set to the value 0) when the circuit is built. So components connected to unused cells would receive the value 0. This is also to make the values shown inside the circuit GUI correspond to the same arrangement of components that was laid out in the designer.

I could either change this, so that the circuit layout is compressed together instead to fill the gaps and the information about what cells where actually used is stored separately. And also disallow components being connected to nothing.

Or just change the cost counting but this would allow exploits to get constants for free.

I think easiest to understand is disallowing connections to empty tiles - and not counting their cost. This would give users the ability to keep the program organized and also have the same position in the GUI later on.